As described in U.S. Pat. No. 4,688,223 issued to Motika and Waicukauski and incorporated herein by reference, complex large scale integrated circuit devices fabricated on a single semiconductor chip contain thousands of functional circuit elements which are inaccessable for discrete testing. Because of the complexity of the internal interconnections and their combinational interdependencies, testing for device integrity becomes even more time consuming as the number of individual components on the die increases. Recently, as the number of circuit elements increases from thousands to hundreds of thousands, the amount of time and storage necessary in testing such components increases even more dramatically than described in the above-identified patent.
Integrated circuits of such complexity are known to be tested by applying random test pattern of logic signals to the inputs to these circuits. The test pattern consists of "1"s and "0"s, with the frequency of occurrence of the "1"s or "0"s on a given primary input being determined by a so-called weighting factor.
As used herein, weighting refers to controlling the relative frequency of "1s" and "0s" in a random sequence of logic signals used to test digital circuits. Thus, for purposes of the present discussion, weighting defines the frequency of the "1" values in this sequence compared to the frequency of the "0" values. A weighting of 9/10 means that 9 "1s" are produced to every "0" produced. When the frequency of "1s" equals the frequency of "0s", the sequence is called non-weighted or uniformly distributed.
Weighting as applied to pseudo-random number generation is expressed in terms of the probability that in a given pattern a "1" or a "0" will be generated. This may be expressed in terms of a ratio or percentage.
In general, testing requires the delivery of certain values, "1"s or "0"s, to the circuit and detecting the response of the circuit. In particular, the values to be delivered to the circuit under test can be carefully calculated (manually or by using test generation programs) in such a way that any anticipated failure of the circuit could be detected by observing the response of the circuit to these values. As is common, vectors or patterns of input values are specifically tailored for detection of anticipated failures of a circuit. As used herein, these vectors are referred to as "tailored vectors".
Contrary to this tailored vectors approach, in a so-called random test system the stimulating input vectors for the circuit under test are generated at random. There are several considerations in favor of random testing approach. First, large memories that are necessary to store tailored vectors are not needed in a random test system. Secondly, tailored vectors are highly focused on the anticipated failures in the logic circuits. With limited knowledge of the physical processes going on during semiconductor manufacturing, and numerous uncontrollable factors that influence these processes, real failures that appear in very large scale integration circuits (VLSI) may be quite different from those anticipated. In that case, test vectors too focused on the limited model of anticipated failures may be of little value. Studies, for example the article by J. Waicukauski and E. Lindbloom entitled Fault Detection Effectiveness of Weighted Random Patterns, in Proceedings of International Test Conference, 1988, pp. 245-249 indicate that given the same level of detection of anticipated failures, random test sequences far exceed the tailored test vectors in their ability to detect unanticipated defects actually observed in the field.
However, a completely random number generation for testing of circuits is simply impossible to implement due to the numbers of combinations of "1"s and "0"s which would adequately test the circuit even for anticipated failures.
The problem with completely random number generation is that there may be circuit elements which will not be tested. This is because exercising these elements requires the coincidence of a large number of random events which will not occur within a practical amount of time.
To overcome this, systems have been developed that change the probabilities for the generation of "1s" or "0s" in the random input signals in such a way that the necessary coincidence happens more frequently. This is done by using a weighted random number generator. By techniques that are well known, a particular weight causes more frequent generation of "1s" or "0s" on a given primary input as necessary for exercising the particular circuit.
The problem with this approach is that many circuits impose conflicting requirements for testing their circuit elements. Thus one element may require a large number of "1s" at a given primary input, where another element may require a larger number of "0s". The Motika et al. patent does not address this issue but rather averages for conflicting requirements. As a result, this system does not permit testing many potential faults.
One possible solution is using different weights for the elements with conflicting requirements, thus creating several sets of input weights. In order to calculate the optimal values of input weights several techniques have been proposed. For example, H. Wunderlich in an article entitled Multiple Distributions for Biased Random Test Patterns, IEEE Transactions on Computer-Aided Design, vol. 9, No. 6, June 1990, pp. 584-593 describes a method based on deriving detection probability equations for anticipated failures and optimizing them. Similar technology is also described by R. Lisanke, F. Brglez, and A. Degeus in an article entitled Testability-Driven Random Test-Pattern Generation published in IEEE Transactions on Computer-Aided Design, Vol. CAD-6, No. 6, November 1987, pp. 1082-1087. This technique is extremely complicated and cannot be used for VLSI with large number of logic elements.
A more realistic approach to calculating multiple sets of weights for random testing of VLSI is based on the use of predefined tailored test vectors that are guaranteed to detect the anticipated failures. In order to guarantee detection of all the anticipated failures, the set of tailored test vectors needs to be divided into subsets which will test different portions of the circuit under test. The division of the tailored vectors into subsets is done in such a way that for each subset one weight can be calculated for every circuit input in such a manner that a weighted random sequence of test signals called "patterns" will contain all tailored test vectors selected for this subset. In order for this to happen, the vectors selected to be placed into a subset have to be similar to each other in that the random weights generated from the selected vectors produce similar test signals. For example, J. Waicukauski, E. Lindbloom, E. Eichelberger, and O. Forlenza in a paper entitled A Method for Generating Weighted Random Test Patterns, in IBM Journal of Research and Development, vol. 33, No. 2, March 1989, pp. 149-161 will allow the vectors selected into a subset to have no more than 5 conflicting values for any inputs of the circuit under test. Similarly, F. Brglez, C. Gloster, G. Kedem in a paper entitled Built-In Self-Test with Weighted Random Pattern Hardware, in the Proceedings of International Conference on Computer Design, 1990, pp. 161-166 requires that the cumulative fault detection probability of all vectors in the subset exceeds 95%. In both cases partitioning of tailored vectors into the subsets and calculation of weights is based on arbitrary requirements that have no justification related to the problem of accurately checking VSCI circuits having large numbers of differing circuits.
More particularly, in these papers the distance from a candidate vector to a subset of already selected vectors is defined as the number of bit positions in the candidate vector where the candidate vector has one logic value, while at least one of the vectors that is already selected into the subset has the opposite logic value.
The problem with such approach is that it does not take into account just how many of the vectors already selected into the subset have a logic value in a given bit position which is opposite to the one in the candidate vector. This can lead to a wrong selection as can be seen from a following example.
Let the original set of tailored vectors be 000, 001, 010, 100, 111, 110, 101, 011. Let the currently selected subset be composed of vectors 000, 001, 010.
According to the distance definition of the above-mentioned paper of J. Waicukauski et al., the closest to this subset out of the remaining vectors is 011, with the distance equal to 2, while obviously 100 has more similarity to those selected vectors in a sense of the possibility of them being included into the same weighted random sequence.